1. Technical Field
The present invention generally relates to a memory device, and more particularly, to a semiconductor memory device.
2. Related Art
In general, a phase change memory device is characterized in that it has a data processing speed almost equal to that of random access memory (RAM) and retains data even when power is off.
The voltage levels of a phase change memory device used when a write operation and a read operation are performed are relatively high. If a memory cell is selected and a write or read operation is performed as described above, a load on a line is increased because a word line WL or a bit line BL is activated within a plurality of cell matrices, with the result that a lot of current is consumed.
Since there is a plurality of current paths, a normal write operation may not be performed because an electric current is not regularly divided according to circumstances. In order to solve this problem, voltage from a write driver can be increased in order to increase current supply force, but reliability of data is deteriorated because a distribution of resistance values is widened due to the resistance of current paths. Accordingly, there is a need for a technique for preventing excessive current consumption and reducing the deterioration of performance due to an increased load on a line.